View CXA2067S_534867.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CXA2067S
Preamplifier for High-Resolution Computer Display
For the availability of this product, please contact the sales office.
Description The CXA2067S is a bipolar IC developed for highresolution computer displays. Features * Wide-band amplifier: 170 MHz@-3 dB (Typ) * Input dynamic range: 1.0 Vp-p (typ) * High gain preamplifier (17 dB) * R, G and B in a single package (SDIP 30 pins) * I2C bus control Contrast control Sub contrast control Brightness control OSD contrast control Cut-off control: 4 channels of DAC output 2 blanking level modes (0.5 V fixed, pedestal -0.3 V) * Sync separator for sync-on-green * Blanking mixing function * OSC mixing function * Video interval detection function * VBLK sync DAC refresh system * 12 V power supply interlocked power saving function Applications High-resolution computer displays Structure Bipolar silicon monolithic IC 30 pin SDIP (Plastic)
Absolute Maximum Ratings (Ta=25 C, GND=0 V) * Supply voltage VCC/R/G/B 14 V VCC 7 V * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 2.05 W Recommended Operating Conditions Supply voltage VCC/R/G/B 120.5 VCC 50.5
V V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
--1--
E99213
CXA2067S
Block Diagram
D/A CONVERTOR SDA
1
I 2 C BUS DECORDER
CUTOFF (R) CUTOFF (G) CUTOFF (B) CUTOFF (RGB)
SCL
2
To each MODE SW
CONTRAST SUB CONTRAST (R) SUB CONTRAST (G) SUB CONTRAST (B) OSD GAIN (R) OSD GAIN (G) OSD GAIN (B) BRIGHTNESS (RGB)
30
CSYNC/VDET
29 12V
VCC R
COF R
3
LPF
28
S/H-R
COF G
4
Rch
SUB CONTRAST CONTRAST GAIN CONTROL DATA
27
ROUT
COF B
5
GAIN CONTROL AMP
BLANKING MODE
26
BRIGHTNESS
GND-R
COF RGB
6
OSD YS GENERATOR
BLANKING BUFFER AMP
25
BLANKING PULSE
S/H-G
RIN
7
5V
OSD GAIN (R)
OSD SW
OSD PULSE (13PIN) YS PULSE (17PIN)
24
GOUT
VCC
8
SYNC SEP/VDET
23
GND-G
GIN
9
12V SYNC SEPARATOR VDET COMPARATOR
SVSW
22
VCC G
SYNC IN
10
21
S/H-B
BIN
11 Gch
20
BOUT
CLP
12
Same as R channel
19
GND-B
OSD-R
13 to OSDSW
18
BLKING
OSD-G
14 to OSDSW
Bch
17 Same as R channel to OSDSW 16 12V
YS
OSD-B
15 to OSDSW
VCC B
--2--
CXA2067S
Pin Description Pin No. Symbol Pin voltage Equivalent circuit
VCC
Description
4k
1
SDA
--
1
I2C bus standard SDA (serial data) input/output. VILMAX=1.5 V VIHMIN=3.5 V VOLMAX=0.4 V
VCC
4k
2
SCL
--
2
I2C bus standard SCL (serial clock) input/output. VILMAX=1.5 V VIHMIN=3.5 V
10k
3 4 5 6
COF R COF G -- COF B COF RGB
3 4 5 6
VCC
VCC VCC 100
VCC
DAC output for cut-off adjustment. Output DC is 1 to 4 V.
VCC 14k
VCC 8k VCC VCC
7
RIN
VCC 1k
9
GIN
1.7 V (Clamp)
7 9
11 300 1k
R, G and B signal inputs. Input via a capacitor.
11
BIN
8
VCC
5V
5 V power supply.
--3--
CXA2067S
Pin No.
Symbol
Pin voltage
Equivalent circuit
Description
VCC VCC 100 VCC
10
SYNC IN
2.8 V
10 150
Sync-on-green signal input. Input via a capacitor.
VCC
VCC 2p
12
CLP
--
12
10k 10k
10k
Clamp pulse (positive polarity) input. VILMAX=0.8 V VIHMIN=2.8 V
VCC
13
OSD-R
VCC 2p
14
OSD-G
--
13 14
5k 10k
OSD control inputs. VILMAX=0.8 V VIHMIN=2.8 V
15
OSD-B
15
16
VCC B
12 V
VCC
12 V power supply. (B channel)
VCC 2p 5k
17
YS
--
17
10k
YS (OSD BLK) control input. VILMAX=0.8 V VIHMIN=2.8 V
--4--
CXA2067S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC VCC 4k VCC
Description
18
BLKING
--
18
30k 10k
Blanking pulse input. Set the V blanking pulse width to 300 s or more. VILMAX=0.8 V VIHMIN=2.8 V
19 23 26 20
GND-B GND-G GND-R BOUT
0V
Ground.
VCCR/G/B VCCR/G/B 2p VCCR/G/B
24
GOUT
--
20 24 5k
310
R, G and B outputs.
27
ROUT
27
21
S/H-B
VCC
VCC 1k
VCC
25
S/H-G
--
21 25 28 300 1k
Brightness sample-and-hold. Connect to GND via a capacitor.
28
S/H-R
22 29
VCC G VCC R
12 V 12 V
12 V power supply. (G channel) 12 V power supply. (R channel)
--5--
CXA2067S
Pin No.
Symbol
Pin voltage
Equivalent circuit
VCC VCC VCC 100 20k 30 500 VCC 5k
Description
30
CSYNC /VDET
--
Sync-on-green signal sync separator output/video detector output. Either of them is selected by SVSW of I2C bus. Typ. : High=4.3 V Low=0.2 V (positive polarity)
--6--
CXA2067S
Definitions of I2C Bus Register Slave Address SLAVE RECEIVER : 40 (HEX) Register Table SUB ADDRESS BIT7 BIT6 00h 01h 0 BLK MODE 02h 03h 04h 05h VDET LEVEL 06h 07h 08h 09h 0Ah VDET OFF SVSW BIT5 BIT4 BIT3 BIT2 CONTRAST BRIGHTNESS CUT OFF R CUT OFF G CUT OFF B OSD GAIN CUT OFF RGB SUB CONTRAST R SUB CONTRAST G SUB CONTRAST B BIT1 BIT0
VSOFF
Note) : don't care Sub Address CONTRAST (8): 0000 Performs the gain control for R, G and B channels in common. Control is performed by the multiplication with SUB CONTRAST. The white balance is adjusted by SUB CONTRAST and the luminance is adjusted by CONTRAST. 0 : Gain minimum (-30 dB or less) 255 : Gain maximum (+17 dB) Switches the blanking level. 0 : Pedestal-0.3 V 1 : 0.3 V fixed
Sub Address BLK MODE (1): 0001
Sub Address BRIGHTNESS (6): Performs the black level control for R, G and B channels in common. 0001 0 : Black level minimum (0.9 V) 63 : Black level maximum (2.8 V) Sub Address CUT OFF R (8): 0010 Performs the Pin 3 (COF R) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Performs the Pin 4 (COF G) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Performs the Pin 5 (COF B) output voltage control. 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) --7--
Sub Address CUT OFF G (8): 0011
Sub Address CUT OFF B (8): 0100
CXA2067S
Sub Address VDET LEVEL (2): 0101
Controls the signal detection (VDET) slice level. 0 : Slice level minimum (RIN or GIN or BIN=30 mV) 1 : Slice level maximum (RIN or GIN or BIN=220 mV) Performs the OSD gain control for R, G and B channels in common. Control is performed by the multiplication with SUB CONTRAST (upper 6 bits) so that the video white balance and tracking are obtained. 0 : Gain minimum (0 Vp-p) 63 : Gain maximum (5 Vp-p)
Sub Address OSD GAIN (6): 0110
Sub Address CUT OFF RGB (8): Performs the Pin 6 (COF RGB) output voltage. 0110 0 : Output voltage minimum (1 V) 255 : Output voltage maximum (4 V) Sub Address SUB CONTRAST R (8): Performs the R channel gain control. 0111 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (-30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST G (8): Performs the G channel gain control. 1000 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (-30 dB or less) 255 : Gain maximum (+17 dB) Sub Address SUB CONTRAST B (8): Performs the B channel gain control. 1001 Control is performed by the multiplication with CONTRAST. Use for the white balance adjustment. 0 : Gain minimum (-30 dB or less) 255 : Gain maximum (+17 dB) Sub Address VDET OFF (1): 1010 Performs the Pin 30 output control. 0 : Output ON 1 : Output OFF Switches the Pin 30 output signal (sync separator/video detector). 0 : Sync separator output 1 : Video detector output Performs the control of VBLK sync DAC refresh function. 0 : Function operation ON 1 : Function operation OFF
Sub Address SV SW (1): 1010
Sub Address VS OFF (1): 1010
--8--
CXA2067S
I2C Bus Logic System No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Item High level input voltage Low level input voltage Low level output voltage with 3 mA SDA current inflow Maximum clock frequency Minimum waiting time for data change Minimum waiting time for data transmission start Low level clock pulse width High level clock pulse width Minimum waiting time for start preparation Minimum data hold time Minimum data preparation time Rise time Fall time Minimum waiting time for stop preparation Symbol VIH VIL VOL fSCL tBUF tHD : STA tLOW tHIGH tSU : STA tHD : DAT tSU : DAT tR tF tSU : STO Min. 3.0 0 0 0 4.0 4.0 4.7 4.0 4.7 0 250 -- -- 4.7 Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. 5.0 1.5 0.4 400 -- -- -- -- -- -- -- 1 300 -- Unit V V V kHz s s s s s ns ns s ns s
--9--
CXA2067S
Electrical Characteristics No. Measurement item 1 2 3 Current consumption (5 V) Current consumption (12 V) Current consumption (12 V OFF) Symbol ICC1 ICC2 ICC3 Measurement contents VCC (5 V) pin inflow current RGB signal input: None VCC R/G/B (12 V) pin inflow current RGB signal input: None VCC pin inflow current for 12 V OFF RGB signal input: None Min. 85 29.5 20 Typ. 115 45 30 Max. 140 55.5 40 Unit mA mA mA
4
Frequency response (50 MHz)
F50
Input the continuous 1 MHz, 50 MHz and 100 MHz sine waves (0.7 Vp-p). Measure the output amplitude gain difference at this time. -1.5 Vout (50 MHz) Gain difference [dB]=20 log Vout (1 MHz) Vout (100 MHz) Gain difference [dB]=20 log Vout (1 MHz)
RGB input signal (RGB input pins)
0
1.9
dB
5
Frequency response (100 MHz)
F100
0.7Vp-p CLP potential (Approx. 1.7 V) GND
-3.0
0
3.0
dB
6
Contrast control 1
Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. GCONT1 GCONT1 : Contrast=SubContrast=FF GCONT2 : Contrast=00/SubContrast=FF
5.6
6.2
--
Vp-p
Input signal
7
Contrast control 2
GCONT2
0.7Vp-p
--
0
100 mVp-p
Measure the output signal amplitude Vout level when a 0.7 Vp-p video signal is input. Contrast=FF/SubContrast=00 8 Sub contrast control GSUB
Input signal 0.7Vp-p
--
0
100 mVp-p
--10--
CXA2067S
No. Measurement item
Symbol
Measurement contents Measure the OSD level of the output signal when the OSD pulse is input. GOSD1 : OSD=3F/SubContrast=FF GOSD2 : OSD=00/SubContrast=FF
OSD interval RGB output signal
Min.
Typ.
Max.
Unit
GOSD1
4.5
5
--
Vp-p
9
OSD gain control
GOSD2
OSD level
--
0
150 mVp-p
VBRT1
Measure the black level of the RGB output signal. VBRT1 : Brightness=00 VBRT2 : Brightness=3F
RGB output signal
0.4
0.7
1
10
Brightness control
V
VBRT2
Black level GND
2.2
2.6
3
BLK control (BLK MODE=0) 11 BLK control (BLK MODE=1)
VBLK1
Measure the BLK level of the output signal when the BLK pulse is input.
--
0.3
0.6
V
BLK level (VBLK1) BLK level (VBLK2) GND
VBLK2
--
0.3
0.6
Sync separator output rise delay 12 Sync separator output fall delay VDET output rise delay 13 VDET output fall delay
SDLYR
Vth=50% Rise Delay Fall Delay
--
30
40 ns
SDLYF
Vth=50%
--
60
80
DDLYR
Vth=50% Rise Delay Vth=50%
0.7Vp-p Fall Delay
--
20
40 ns
DDLYF
--
30
60
--11--
CXA2067S
No. Measurement item DAC output voltage (COFF=00) DAC output voltage (COFF=FF)
Symbol
Measurement contents
Min.
Typ.
Max.
Unit
VCUT1 Measure the DAC output voltage (Pin 6) for COFF=00/FF. VCUT2
--
1
1.3 V
14
3.9
4
--
15
VDET output amplitude
Input the crosshatch signal of DotClock=100 MHz/0.7 Vp-p and measure the VDET output amplitude. SW SW=1/VDET LEVEL=0 VDET
Input signal 0.7Vp-p
3.85
4
--
Vp-p
10ns
10ns
--12--
CXA2067S
Electrical Characteristics Measurement Circuit
SYNC SEP/VDET Output
1
I 2 C BUS 220
SDA
CSYNC/VDET
30 47F 12V
2
220
SCL
VCC R
29 0.1F
3
COF R
S/H-R
28 0.1F
4
DAC Output
COF G
ROUT
27 Rch Output
5
COF B
GND-R
26
6
0.1F
COF RGB
S/H-G
25 0.1F
7
75 47F
RIN
GOUT
24 Gch Output
8
5V 0.1F
VCC
GND-G
23 47F 12V
9
0.1F 75
GIN
VCC G
22 0.1F
10 SYNC IN 0.1F 75 11 BIN 0.1F 75 12 CLP
S/H-B
21 0.1F
BOUT
20 Bch Output
GND-B
19
13 OSD-R
BLKING
18
14 OSD-G
YS
17 47F 12V
15 OSD-B
VCC B
16 0.1F
--13--
CXA2067S
Electrical Characteristics Measurement Circuit (Frequency response)
SYNC SEP/VDET Output
1
I 2 C BUS 220
SDA
CSYNC/VDET
30 47F 12V
2
220
SCL
VCC R
29 0.1F
3
COF R
S/H-R
28 0.1F
4
DAC Output
COF G
ROUT
27 Rch Output
5
COF B
GND-R
26
6
0.1F
COF RGB
S/H-G
25 0.1F
7
75 47F
RIN
GOUT
24 Gch Output
8
5V 0.1F
VCC
GND-G
23 47F 12V
9
0.1F 75
GIN
VCC G
22 0.1F
10 SYNC IN 0.1F 11 BIN 0.1F 12 CLP
S/H-B
21 0.1F
BOUT
20 Bch Output
GND-B
19
13 OSD-R
BLKING
18
14 OSD-G
YS
17 47F 12V
15 OSD-B
VCC B
16 0.1F
--14--
VBLK Sync DAC Refresh System
VBLK
Transmission interval Data 2 Data 3
Bus data transmission
Data 1
enable
DAC refresh Enable signal
disable
--15--
DAC rewrite is not performed when the bus data transmission is in progress for the VBLK interval. The sent data is hold. Rewrite to Data 3. When Data 3 is not transmitted, rewrite to Data 2. CXA2067S
DAC refresh signal
The latest data which was sent before VBLK is written to DAC. In this case, Data 1 is written.
The VBLK signal is extracted form the composite BLK signal input to Pin 18. The DAC data rewrite for each control is simultaneously performed, synchronizing to the VBLK signal. The received I2C bus data is held by the latch till the next VBLK signal comes. Therefore, the timing of I2C bus data transmission from the microcomputer is free. The V blanking pulse width input to Pin 18 should be 300s or more.
CXA2067S
Application Circuit
SYNC SEP/VDET Output
1
I 2 C BUS 220
SDA
CSYNC/VDET
30 47F 12V
2
220
SCL
VCC R
29 0.1F
3
COF R
S/H-R
28 0.1F
4
DAC Output
COF G
ROUT
27 Rch Output
5
COF B
GND-R
26
6
0.1F
COF RGB
S/H-G
25 0.1F
7
47F
RIN
GOUT
24 Gch Output
8
5V 0.1F
VCC
GND-G
23 47F 12V
9
0.1F 0.1F
GIN
VCC G
22 0.1F
10 SYNC IN
S/H-B
21 0.1F
11 BIN 0.1F 12 CLP
BOUT
20 Bch Output
GND-B
19
13 OSD-R
BLKING
18
14 OSD-G
YS
17
YS input 47F 12V
15 OSD-B
VCC B
16 0.1F
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
--16--
CXA2067S
Notes on Operation 1. The ROUT, GOUT and BOUT outputs should be received in the high impedance state. 2. The wiring from ROUT, GOUT and BOUT to the power amplifier should be as short as possible. 3. For the decoupling capacitors for VCC and VCC R/G/B, the ceramic capacitor and the electrolysis capacitor should be connected in parallel as closely to the IC as possible. 4. The clamp capacitors for RIN, GIN, BIN, S/H R, S/H G and S/H B should be connected as close to the IC as possible. 5. The signals to RIN, GIN and BIN should be input via a clamp capacitor with the low impedance. 6. Set the output OFF when the VDET output is not used (The cross talk may deteriorate).
--17--
CXA2067S
Package Outline
Unit : mm
30PIN SDIP (PLASTIC)
+ 0.4 26.9 - 0.1
30
16
+ 0.3 8.5 - 0.1
+ 0.1 .05 0.25 - 0
15 1.778
1
0.5 MIN
+ 0.4 3.7 - 0.1
10.16
0 to 15
Two kinds of package surface: 1.All mat surface type. 2.All mirror surface type.
0.5 0.1 0.9 0.15
PACKAGE STRUCTURE
MOLDING COMPOUND SONY CODE EIAJ CODE JEDEC CODE SDIP-30P-01 SDIP030-P-0400 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING COPPER ALLOY 1.8g
--18--
3.0 MIN
Sony Corporation

▲Up To Search▲

Price & Availability of CXA2067S

	To Download CXA2067S Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .